The subject system and method are generally directed to parametrically integrating static and dynamic analyses conducted in connection with an electronic design cycle. The system and method provide automated measures for the intercoupling of static and dynamic analyses by the synergistic exchange of parametric data therebetween, whereby such static analyses as for electronic circuit timing and such dynamic analyses as for simulation-based electrical integrity are enhanced in concert. The system and method thereby enable systematic verification and optimization of an electronic system design.
With the ongoing trend of electronic system implementations growing in sophistication and complexity, it is increasingly important to quickly and accurately analyze different aspects of an electronic system's operation at various stages of its electronic design cycle. For example, a static timing analysis (STA) is normally conducted during an early stage of the design cycle without simulation, in order to obtain a fast yet reasonably accurate measure of timing in the electronic system design. Later in the design cycle, various electrical integrity analyses, such as a signal integrity (SI) analysis, are normally conducted using simulation based on behavioral modeling of the given portion(s) of the electronic system design. These static and dynamic analyses, however, are typically conducted in ad hoc manner, during their different stages of the design cycle, without any intercoupling therebetween. There is no automated coordination of the respective analysis tools to assist and enhance the operation of one in light of the other. Consequently, there is no provision for optimizing the electronic design at hand, though the use of the analysis tools may preserve compliance with the applicable constraints at different stages of design.
In the absence of sufficient integration measures in this regard, designers have tended to simply make ad hoc use of the available analysis and verification tools. This has lead to design flow inefficiencies yielding less than optimal designs. For example, designers would often carry out manual timing-checks, using hand-calculations at times to prepare for proper post-layout verification using simulation. Unfortunately, the goal in such exercises is to just ensure satisfaction of the many applicable constraints, rather than ensuring optimal design by providing sufficient margins on all constraints. Moreover, the manual calculations of timing-budget are not only time-consuming and prone to error, they fail to adequately reflect dynamic SI effects that would arise during actual operation of the electronic system under design.
Designers would also just resign themselves to following application notes of particular device manufacturers and employ pre-defined layout constraints based on layout rules they prescribe. Rigid adherence to universal specifications and recommendations such as these, however, tends to inhibit flexibility in design. Designers taking this approach may be averse to varying component selection to include those of different vendors, or to considering other variations such as in board dimensions and circuit configurations. The broad applicability inherent to manufacturers' specifications and recommendations is also likely to reflect aspects of conservative over-design, which may be good for sustained operability under wide ranges of conditions but bad for optimization of the design at hand.
EDA vendors have provided so-called design-in-kits to enable IC/package/PCB co-design, and have demonstrated the use of SI and static timing analysis tools. While such design-in-kits heretofore known in the art provide a set of models, methods, automation and reference designs (of certain IP cores) which help to make for faster design cycle, they facilitate but a piece-meal approach to the use of their resources, offering no systematic methodology by which a designer is guided to make synergistic inter-coupled use of the same. The kits' capabilities are made available for use in isolation to verify compliance with constraints at different stages of design, but not in any parametrically integrated manner sufficient to guide a methodical approach also towards optimal design.
Designers are thus left with using the design-in kit content and analysis tools in the same ad-hoc ways they are accustomed to using verification and analysis tools in a typical design cycle. While various analysis tools—such as for static timing analysis (based on transaction-based timing models) and dynamic SI analysis (based on real-time circuit simulations)—may be at their disposal, designers are not guided with any coordinated data exchange between the static and dynamic analysis tools. Hence, practicable measures for timing-closure with pre-route and post-route SI simulations are not readily available. While real-time simulation resources may be available on comprehensive design and analysis platforms for use in more exhaustive timing-verification, conducting such exhaustive timing verification at an SI or other electrical integrity analysis stage is much too time-consuming and difficult to be practicable in most applications.
There is therefore a need for a system and method which automatically coordinate parametric integration of static and dynamic analyses in an electronic design cycle for the synergistic enhancement of both. There is a need for an automated approach whereby such static analyses as static timing analysis (STA) may be intercoupled in operation with such dynamic analyses as simulation-based signal integrity analysis (SI), so that the electronic system design may be efficiently optimized while being verified in performance.